This technology enables concurrent software development at all levels, including ROM code, firmware code, device driver, OS porting, middleware and application development. Typically, a VPE focuses on the functional aspects of the hardware like functionality, memory maps, interconnects, etc , and typically avoids hardware details that are not exposed through the software programming model like timing details, power dissipation, etc. However, these details can be included at the expense of simulation speed. Table 1. Modeling focus is on the interaction and impact between the software and the functionality of the peripheral.
Applications of a VPE A VPE is typically used for studying the architecture for different parameters, performing performance measurements, develop and debug of embedded software, etc. An eSW developer can actually develop the application focusing on a unique architecture or satisfying a family of architecture.
Also, the eSW can be tested for its applicability in different system architecture. An indication of the configuration parameters for models of typical IPs can be had from Table 1. Typical statistics measured for a model are listed in Table 2. Software Develop and Debug VPE enables system-level software development as it uses the simulation models of the target processors.
In order to have effective software development, it is necessary that the VPE simulates at a fast speed and allows software debug.
It is becoming more and more common for several cores to be integrated to form a system-on-chip SoC in order to achieve optimum functionality and performance. The debugging of SoC designs containing several cores places new demands on development tools and necessitates a multi-core debugger MCD. An MCD allows debugging multiple core-models and hardware by synchronizing the operation of all cores during debug.
Complex, multi-core systems can be stopped quickly to preserve critical state information, by providing a powerful cross core breakpoint facility that enables a breakpoint on one core to stop all other cores in the system. DSP, TriMedia, etc. The first design has been made largely depending on protocol decoding in hardware. Going forward, a more flexible design is required based on software implementations running on a vector processor.
To prove the architecture in an early stage of the design-cycle, it is necessary to analyse the system design by developing and executing MCeSW over it. Figure 3 shows the logical block-diagram of the modeled architecture. Fig 3. Linux and Windows dev. Under this full system-load, the ARM subsystem is executing 70 Kilo-inst-per-second. This is a time faster than similar RTL-simulation. Conclusions This paper highlighted a methodology for exploring multi-core system-level architecture and developing software even in the absence of target hardware.
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As a concrete use-case, this paper presented a complex VPE developed for the multi-core telecom subsystem. The VPE is being successfully used within NXP for the multi-core embedded software development and architecture exploration. All of this happens while the architectural spec and hardware design are still being finalized! References  A.
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Electronic Systems on Chip
List your Products Suppliers, list your IPs for free. List your Products. Memory size, memory type, memory delay, arbitration scheme, etc Cache controller: L2 cache sizes, caching scheme.
Hardcover ISBN: Imprint: Morgan Kaufmann. Published Date: 28th September Page Count: View all volumes in this series: Systems on Silicon.
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